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mosel vitelic 1 v53c316405a 3.3 volt 4m x 4 edo page mode cmos dynamic ram v53c316405a rev. 1.2 march 1998 v53c316405a 50 60 max. ras access time, (t rac ) 50 ns 60 ns max. column address access time, (t caa ) 25 ns 30 ns min. extended data out page mode cycle time, (t pc ) 20 ns 25 ns min. read/write cycle time, (t rc ) 84 ns 104 ns features n 4m x 4-bit organization n edo page mode for a sustained data rate of 50 mhz n ras access time: 50, 60 ns n low power dissipation n read-modify-write, ras -only refresh, cas -before-ras refresh and hidden refresh n refresh interval: 4096 cycles/64 ms n available in 24/26-pin 300 mil soj, and 24/26-pin 300 mil tsop-ii n single +3.3v 0.3v power supply n ttl interface description the v53c316405a is a 4,194,304 x 4 bit high- performance cmos dynamic random access mem- ory. the v53c316405a offers page mode opera- tion with extended data output. the v53c316405a has asymmetric address, 12-bit row and 10-bit col- umn. all inputs are ttl compatible. edo page mode operation allows random access up to 1024 x 4 bits, within a page, with cycle times as short as 20ns. these features make the v53c316405a ideally suited for a wide variety of high performance com- puter systems and peripheral applications. device usage chart operating temperature range package outline access time (ns) power temperature mark k t 50 60 std. 0 c to 70 c ? ? blank
2 mosel vitelic v53c316405a v53c316405a re v . 1.2 march 1998 pin names a 0 ? 11 row, column address inputs ras row address strobe cas column address strobe we write enable oe output enable i/o 1 ?/o 4 data input, output v cc +3.3v supply v ss 0v supply nc no connect 24/26-pin plastic soj/tsop-ii pin configuration top view we ras i/o 1 i/o 2 a 0 a 1 a 2 a 3 v cc v cc 1 2 3 4 5 9 10 11 12 13 26 25 24 23 22 18 17 16 15 14 v i/o i/o cas oe a a a a v ss 4 3 7 a 10 311640500-02 19 a 8 9 6 5 4 ss 6 21 a a 11
3 mosel vitelic v53c316405a v53c316405a re v . 1.2 march 1998 absolute maximum ratings* operating temperature range .................. 0 to 70 c storage temperature range ............... -55 to 150 c input/output voltage .... -0.5 to min (v cc +0.5, 4.6) v power supply voltage .......................... -1.0 to 4.6 v power dissipation .......................................... 0.5 w data out current (short circuit) ...................... 50 ma *note: operation above absolute maximum ratings can adversely affect device reliability. capacitance* t a = 25 c, v cc = 3.3 v 0.3v, v ss = 0 v *note: capacitance is sampled and not 100% tested. symbol parameter typ. max. unit c in1 address input 5 pf c in2 ras , cas , we , oe 7 pf c out data input/output 7 pf block diagram no . 2 cloc k gener ator data in buff er data out buff er column address buff ers (10) refresh controller ro w decoder refresh counter (12) no . 1 cloc k gener ator v oltage do wn gener ator ro w address buff ers (11) 10 4 i/o1 i/o2 i/o3 i/o4 4 oe 12 12 12 4 4096 vcc vcc (inter nal) 1024 x4 memor y arr a y 4096 x 1024 x 4 sense amplifier i/o gating column decoder a0 cas we a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 ras 10 311640502-04 4096 x 4
4 v53c316405a re v . 1.2 march 1998 mosel vitelic v53c316405a dc and operating characteristics (1-2) t a = 0 c to 70 c, v cc = 3.3 v 0.3v, v ss = 0 v, v t = 2ns unless otherwise specified. symbol parameter access time v53c316405a unit test conditions notes min. typ. max. i li input leakage current (any input pin) ?0 10 m a v ss v in v cc +0.3v 1 i lo output leakage current (for high-z state) ?0 10 m a v ss v out v cc +0.3v ras , cas at v ih 1 i cc1 v cc supply current, operating 50 50 ma t rc = t rc (min.) 2, 3, 4 60 40 i cc2 v cc supply current, ttl standby 2 ma ras , cas at v ih other inputs 3 v ss i cc3 v cc supply current, ras -only refresh 50 50 ma t rc = t rc (min.) 2, 4 60 40 i cc4 v cc supply current, edo page mode operation 50 35 ma minimum cycle 2, 3, 4 60 30 i cc5 v cc supply current, during cas -before- ras refresh 50 50 ma 2, 4 60 40 i cc6 v cc supply current, cmos standby 1.0 ma ras 3 v cc ?0.2 v, cas 3 v cc ?0.2 v, other input pins 3 v ss 1 v cc power supply voltage 3.0 3.3 3.6 v v il input low voltage ?.5 0.8 v 1 v ih input high voltage 2.0 v cc + 0.5 v 1 v ol ttl output low voltage 0.4 v i ol = 2 ma 1 v oh ttl output high voltage 2.4 v i oh = ? ma 1 v ol cmos output low voltage 0.2 v i ol = 100 m a 1 v oh cmos output high voltage v cc ?0.2 v i oh = ?00 m a 1
5 mosel vitelic v53c316405a v53c316405a re v . 1.2 march 1998 ac characteristics (5,6) t a = 0 to 70 ?c, v cc = 3.3 v 0.3v, t t = 2 ns # symbol parameter -50 -60 unit note min. max. min. max. common parameters 1 t rc random read or write cycle time 84 104 ns 2 t rp ras precharge time 30 40 ns 3 t ras ras pulse width 50 10k 60 10k ns 4 t cas cas pulse width 8 10k 10 10k ns 5 t asr row address setup time 0 0 ns 6 t rah row address hold time 8 10 ns 7 t asc column address setup time 0 0 ns 8 t cah column address hold time 8 10 ns 9 t rcd ras to cas delay time 12 37 14 45 ns 10 t rad ras to column address delay 10 25 12 30 ns 11 t rsh ras hold time 13 15 ns 12 t csh cas hold time 40 50 ns 13 t crp cas to ras precharge time 5 5 ns 14 t t transition time (rise and fall) 1 50 1 50 ns 7 15 t ref refresh period 64 64 ms read cycle 16 t rac access time from ras 50 60 ns 8, 9 17 t cac access time from cas 13 15 ns 8, 9 18 t caa access time from column address 25 30 ns 8,10 19 t oea oe access time 13 15 ns 20 t ral column address to ras lead time 25 30 ns 21 t rcs read command setup time 0 0 ns 22 t rch read command hold time 0 0 ns 11 23 t rrh read command hold time referenced to ras 0 0 ns 11 24 t clz cas to output in low-z 0 0 ns 8 25 t off output buffer turn-off delay 0 13 0 15 ns 12 26 t oez output turn-off delay from oe 0 13 0 15 ns 12 27 t dzc data to cas low delay 0 0 ns 13 28 t dzo data to oe low delay 0 0 ns 13 29 t cdd cas high to data delay 10 13 ns 14 30 t odd oe high to data delay 10 13 ns 14
6 v53c316405a re v . 1.2 march 1998 mosel vitelic v53c316405a write cycle 31 t wch write command hold time 8 10 ns 32 t wp write command pulse width 8 10 ns 33 t wcs write command setup time 0 0 ns 15 34 t rwl write command to ras lead time 13 15 ns 35 t cwl write command to cas lead time 13 15 ns 36 t ds data setup time 0 0 ns 16 37 t dh data hold time 8 10 ns 16 read-modify-write cycle 38 t rwc read-write cycle time 113 138 ns 39 t rwd ras to we delay time 64 77 ns 15 40 t cwd cas to we delay time 27 32 ns 15 41 t awd column address to we delay time 39 47 ns 15 42 t oeh oe command hold time 10 13 ns edo page mode cycle 43 t pc edo page mode cycle time 20 25 ns 44 t cp cas precharge time 8 10 ns 45 t cpa access time from cas precharge 27 32 ns 7 46 t coh output data hold time 5 5 ns 47 t ras ras pulse width in edo mode 50 200k 60 200k ns 48 t rhpc cas precharge to ras delay 27 32 ns t des oe setup time prior to cas 5 5 ns edo page mode read-modify-write cycle 49 t prwc edo page mode read-write cycle time 58 68 ns 50 t cpwd cas precharge to we 41 49 ns cas -before- ras refresh cycle 51 t csr cas setup time 10 10 ns 52 t chr cas hold time 10 10 ns 53 t rpc ras to cas precharge time 5 5 ns 54 t wrp write to ras precharge time 10 10 ns 55 t wrh write hold time referenced to ras 10 10 ns ac characteristics (5,6) t a = 0 to 70 ?c, v cc = 3.3 v 0.3v, t t = 2 ns # symbol parameter -50 -60 unit note min. max. min. max.
7 mosel vitelic v53c316405a v53c316405a re v . 1.2 march 1998 cas -before- ras counter test cycle 56 t cpt cas precharge time 35 40 ns test mode 60 t wts write command setup time 10 10 ns 61 t wth write command hold time 10 10 ns 62 t chrt cas hold time 30 30 ns 63 t raht ras hold time 30 30 ns ac characteristics (5,6) t a = 0 to 70 ?c, v cc = 3.3 v 0.3v, t t = 2 ns # symbol parameter -50 -60 unit note min. max. min. max.
8 v53c316405a re v . 1.2 march 1998 mosel vitelic v53c316405a notes: 1) all voltages are referenced to v ss . 2) i cc1 , i cc3 , i cc4 and i cc5 depend on cycle rate. 3) i cc1 and i cc4 depend on output loading. specified values are obtained with the output open. 4) address can be changed once or less while ras = v il . in case of icc4 it can be changed once or less during a edo page mode cycle 5) an initial pause of 200 m s is required after power-up followed by 8 ras cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. in case of using the internal refresh counter, a minimum of 8 cas -before- ras initialization cycles instead of 8 ras cycles are required. 6) ac measurements assume t t = 2 ns. 7) v ih (min.) and v il (max.) are reference levels for measuring timing of input signals. transition times are also measured between v ih and v il . 8) measured with the specified current load and 100 pf at v ol = 0.8 v and v oh = 2.0 v. access time is determined by the latter of t rac , t cac , t caa ,t cpa , t oea . t cac is measured from tristate. 9) operation within the t rcd (max.) limit ensures that t rac (max.) can be met. t rcd (max.) is specified as a reference point only. if t rcd is greater than the specified t rcd (max.) limit, then access time is controlled by t cac . 10) operation within the t rad (max. ) limit ensures that t rac (max.) can be met. t rad (max.) is specified as a reference point only. if t rad is greater than the specified t rad (max.) limit, then access time is controlled by t caa . 11) either t rch or t rrh must be satisfied for a read cycle. 12) t off (max.) , t oez (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. t off is referenced from the rising edge of ras or cas , whichever occurs last. 13) either t dzc or t dzo must be satisfied. 14) either t cdd or t odd must be satisfied. 15) t wcs , t rwd , t cwd and t awd are not restrictive operating parameters. they are included in the data sheet as electrical characteristics only. if t wcs > t wcs (min.) , the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle; if t rwd > t rwd (min.) , t cwd > t cwd (min.) and t awd > t awd (min.) , the cycle is a read-write cycle and i/o will contain data read from the selected cells. if neither of the above sets of conditions is satisfied, the condition of i/o (at access time) is indeterminate. 16) these parameters are referenced to the cas leading edge in early write cycles and to the we leading edge in read- write cycles.
9 mosel vitelic v53c316405a v53c316405a re v . 1.2 march 1998 waveforms of read cycle row column row valid data out ras cas address we oe i/o (inputs) i/o (outputs) v ih v il t ras t rc t csh t rad t cas t rp t rah t crp t rsh t rcd t ral t asr t cah t asc t asr t rch t rrh t rcs t caa t oea t clz t cac t oez t odd t cdd t off t dzc t dzo t rac hi z hi z ?? or ? wl1 v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol
10 v53c316405a re v . 1.2 march 1998 mosel vitelic v53c316405a waveforms of write cycle (early write) ras cas address we oe i/o (inputs) i/o (outputs) . t ras valid data in hi z column row row ?? or ? wl2 t rc t rp t csh t rcd t rsh t cas t crp t ral t rad t asr t asc t cah t asr t cwl t rah t wcs t wp t wch t rwl t dh t ds v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol
11 mosel vitelic v53c316405a v53c316405a re v . 1.2 march 1998 waveforms of write cycle ( oe controlled write) valid data t rwl t wp t oeh t cwl row ?? or ? hi-z hi-z column row t asc t rad t ral t cah t rah ras cas address we oe i/o (inputs) i/o (outputs) . t cas t rsh t rcd t asr t asr wl3 v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il v ih v il t rc t ras t rp t csh t csh t odd t dzo t dzc t dh t ds t oez t clz t oea
12 v53c316405a re v . 1.2 march 1998 mosel vitelic v53c316405a waveforms of read-write (read-modify-write) cycle row row t rwc i/o (outputs) i/o (inputs) oe we column valid data in data out t rac ?? or ? ras cas address wl4 v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v ol v oh t ras t rp t csh t rcd t rsh t cas t crp t asr t cah t asc t rah t asr t rad t awd t cwd t rwd t cwl t rwl t wp t oeh t caa t oea t rcs t ds t dh t dzo t dzc t clz t cac t odd t oez
13 mosel vitelic v53c316405a v53c316405a re v . 1.2 march 1998 waveforms of edo page mode read cycle t rp column 2 row data out ras i/o we address cas v ih v il ?? or ? oe t ras (output) data out column n column 1 data out 1 2 n wl5 v ih v il v ih v il v ih v il v oh v ol v ih v il t rhpc t rcd t crp t pc t cas t cp t cas t rsh t cas t crp t crh t ral t asr t rah t asc t cah t asc t cah t asc t cah t rad t rcs t rrh t rch t cac t caa t cpa t oes t cpa t caa t off t oea t rac t cac t caa t clz t coh t coh t oez t cac
14 v53c316405a re v . 1.2 march 1998 mosel vitelic v53c316405a waveforms of edo page mode early write cycle column 1 column 2 row addr data in n data in 2 data in 1 column n ras i/o (input) we address cas ?? or ? oe t ras wl8 v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il t rcd t rhpc t rp t crp t pc t cas t cp t cas t cas t crp t rsh t ral t cah t asc t cah t asc t cah t csh t asc t rah t asr t rad t cwl t wch t wp t wcs t wp t wp t wch t wch t wcs t wcs t cwl t cwl t rwl t ds t dh t dh t ds t dh t ds
15 mosel vitelic v53c316405a v53c316405a re v . 1.2 march 1998 waveforms of edo page mode late write and read-modify-write cycle t odd ras cas we oe address i/o (inputs) i/o (outputs) data in data in data in data out out data data out row column column row column wl17 t ras v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t prwc t csh t rcd t cas t cas t cas t rsh t rp t crp t asr t ral t cah t asc t cah t asc t cah t asc t rad t rah t asr t rwl t cwl t cpwd t cwd t cwl t cwd t cpwd t cwl t cwd t rwd t rcs t awd t caa t oea t awd t oea t wp t wp t awd t wp t rac t dzo t cac t dzc t clz t odd t oez t ds t dh t oeh t dzc t cpa t caa t clz t odd t oez t ds t dh t dzc t cpa t clz t oeh t cac t caa t ds t dh t oeh t oea
16 v53c316405a re v . 1.2 march 1998 mosel vitelic v53c316405a waveforms of ras only refresh cycle row row hi-z address ras cas i/o (outputs) ?? or ? wl9 v ih v il v ih v il v ih v il v oh v ol t rc t ras t rp t crp t rpc t asr t asr t rah
17 mosel vitelic v53c316405a v53c316405a re v . 1.2 march 1998 waveforms of cas -before- ras refresh cycle t rc hi-z ?? or ? ras i/o (outputs) i/o (inputs) oe we cas wl10 v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rp t rp t rpc t csr t cp t chr t rpc t crp t wrp t wrh t oez t cdd t odd t off
18 v53c316405a re v . 1.2 march 1998 mosel vitelic v53c316405a waveforms of hidden refresh read cycle ras i/o (outputs) i/o (inputs) oe we address cas ?? or ? valid data out row column row hi-z wl11 v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t rc t rc t ras t rp t ras t rp t rcd t rsh t chr t crp t rad t asc t rah t asr t cah t wrp t wrh t asr t rrh t rcs t caa t oea t dzc t dzo t cdd t odd t off t oez t cac t clz t rac
19 mosel vitelic v53c316405a v53c316405a re v . 1.2 march 1998 waveforms of hidden refresh early write cycle ras i/o (output) i/o (input) we address cas ?? or ? t rc row row valid data hi-z column wl12 v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t ras t rp t rcd t rsh t rc t ras t rp t crp t chr t rad t rah t asr t asc t cah t asr t wcs t wch t wp t wrp t wrh t ds t dh
20 v53c316405a re v . 1.2 march 1998 mosel vitelic v53c316405a waveforms of cas -before- ras refresh counter test cycle t ras ras i/o (inputs) oe we address cas i/o (outputs) i/o (outputs) i/o (inputs) we oe column row data out data in hi-z read cycle: write cycle: v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol v ih v il v ih v il v ih v il v ih v il t rp t csb t chr t cp t rsh t cas t ral t cah t asc t asr t wrp t caa t rrh t rch t cac t rcs t oea t wrh t dzc t dzo t clz t cdd t odd t off t oez t wrp t wcs t wrh t rwl t cwl t wch t dh t ds
21 mosel vitelic v53c316405a v53c316405a re v . 1.2 march 1998 waveforms of test mode entry i/o (outputs) i/o (inputs) oe we cas ras ?? or ? hi-z address row wl15 hi-z v ih v il v ih v il v ih v il v ih v il v ih v il v ih v il v oh v ol t rp t rc t ras t rp t rpc t cp t csr t chrt t rpc t crp t asr t raht t wts t wth t odd t cdd t oez t off
22 v53c316405a re v . 1.2 march 1998 mosel vitelic v53c316405a block diagram in test mode normal test vcc vss i/o 3 normal test vcc vss i/o 2 normal test vcc vss i/o 1 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block 1 m block i/o 4 i/o 3 i/o 2 i/o 1 normal test normal normal normal test test test a0c,a1c a0c,a1c a0c,a1c a0c,a1c a0c,a1c a0c,a1c a0c,a1c a0c,a1c normal test vcc vss i/o 4 test mode as the v53c316405a is organized internally as 4m x 4-bits, a test mode cycle using 4:1 compression can be used to improve test time. note that in the 4m x 4 version the test time is reduced by 1/4 for a n test pattern. in a test mode ?rite?the data from each i/o pin is written into four 1m blocks simultaneously (all ??s or all ??s). in test mode ?ead?each i/o output is used for indicating the test mode result. if the internal four bits are equal, the i/o would indicate a ?? if they were not equal, the i/o would indicate a ?? the wcbr cycle ( we , cas before ras ) puts the device into test mode. to exit from test mode, a cas be- fore ras refresh? ras only refresh?or ?idden re- fresh?can be used.refresh during test mode operation can be performed by normal read cycles or by wcbr refresh cycles. row addresses a0 through a11 have to kept high to perform a testmode entry cycle. all other address- es are don? care.
23 mosel vitelic v53c316405a v53c316405a re v . 1.2 march 1998 package diagrams 24/26-pin 300 mil soj 24/26-pin 300 mil tsop-ii index marking units in inches [mm] 30 26 21 14 19 1 6 13 8 a does not include plastic or metal protrusion of 0.15 max. per side 0.020 [0.5] 0.315 min [0.8] min 0.6 [15.24] 0.680 -0.009 [17.27 -0.25 ] 0.104 0.003 [2.64 0.1 ] 0.148 -0.020 [3.75 -0.5 ] 0.008 +0.003 [0.2 +0.1 ] 0.335 [0.85] max 0.305 -0.009 [7.75 -0.25 ] 0.340 -0.009 [8.63 -0.25 ] 0.268 0.008 [6.8 0.2 ] 1 m 0.020 -0.003 [0.51 -0.1 ] 0.007 [0.18] 24x m .05 [1.27] b [0.003] 0.1 0.009 [0.25] a 0.009 [0.25] b 0.007 [0.18] b 1 1 26 14 1 13 0.4 +0.12 ?.1 0.016 +0.005 ?.004 0.006 +0.003 ?.004 0.15 +0.08 ?.09 5 max. 0.008 [0.2] 24x m unit in inches [mm] 0.006 0.002 [0.15 0.05] 0.05 [1.27] 0.039 0.002 [1.0 0.05] 0.3 0.005 [7.62 0.13] 0.363 0.008 [9.22 0.2] 0.050 max [1.27 max] 0.004 [0.1] 0.680 0.005 [17.27 0.13] does not include plastic or metal protrusion of 0.15 max. per side 1 1 0.024 -0.008 [0.6 -0.2 ]
mosel vitelic w orld wide offices v53c316405a ?cop yr ight 1998, mosel vitelic inc. 3/98 pr inted in u .s .a. mosel vitelic 3910 n. first street, san jose , ca 95134-1501 ph: (408) 433-6000 f ax: (408) 433-0952 tlx: 371-9461 u .s. sales offices the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 hong kong 19 dai fu street taipo industrial estate taipo, nt, hong kong phone: 852-2665-4883 fax: 852-2664-7535 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 1 creation road i science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-578-3344 fax: 886-3-579-2838 japan wbg marine west 25f 6, nakase 2-chome mihama-ku, chiba-shi chiba 261-71 phone: 81-43-299-6000 fax: 81-43-299-6555 ireland & uk block a unit 2 broomfield business park malahide co. dublin, ireland phone: +353 1 8038020 fax: +353 1 8038049 germany (continental europe & israel ) 71083 herrenberg benzstr. 32 germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0185 northeastern suite 436 20 trafalgar square nashua, nh 03063 phone: 603-889-4393 fax: 603-889-9347 southwestern suite 200 5150 e. pacific coast hwy. long beach, ca 90804 phone: 562-498-3314 fax: 562-597-2174 central & southeastern 604 fieldwood circle richardson, tx 75081 phone: 972-690-1402 fax: 972-690-0341

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